1. Field of the Invention
The present invention generally relates to integrated circuit storage devices and more particularly to an improved manufacturing method and structure that prevents unintended short circuits between gate electrodes and bitline contacts.
2. Description of the Related Art
As the technology surrounding integrated circuit storage structure progresses, there is a need to continually reduced the size of the storage structures so as to increase the density per given area of integrated circuit chip. Some conventional storage structures included a storage device such as a deep trench capacitor and an adjacent tansistor that controls access to the deep trench capacitor. However, in an effort to continue the reduction in the size of storage structures, recent trench capacitors have included vertical transistors adjacent the sides of the deep trench capacitor. Such storage devices include a gate conductor/contact in the upper portion of the deep trench. There are a number of different wiring structures and conductive connections adjacent to the storage devices, such as bitline contacts.
However, such conventional devices suffer from the disadvantage that if the gate contact or any surrounding conductive structure are not properly aligned, the misalignment may cause an unintended electrical connection between the gate contact and the adjacent structure. For example, if the gate contact is misaligned there may be an unintended short circuit between the contact bitline and the gate contact.
Therefore, there is a need for an improved manufacturing method and structure which reduces or eliminates the possibility of a short circuit between the gate contact and the bitline contact, even if slight misalignment occurs. The invention described below addresses this problem and provides a novel structure and manufacturing method that eliminates or reduces the probability of a short circuit between the gate contact and adjacent structures.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional storage structures the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved storage structure.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention a memory cell having a trench capacitor and a vertical transistor adjacent to the capacitor which also includes a vertical gate conductor above the trench capacitor having an upper portion with a width less than the lower portion of the gate conductor. The memory cell further includes spacers adjacent to the upper portion of the gate conductor with a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor. The spacers are silicon nitride and share a border with the bitline contact.